A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms

A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms

Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghiyan, Farhad Mehdipour


Reconfigurable computing offers advantages over traditional hardware and software implementation of computational algorithms. It is based on using reprogrammable devices, which can be reconfigured after fabrication to implement the desired algorithm. Reconfigurable computing systems can take advantage of hardware but still maintains the flexibility of software. Particular applications, including encryption, are specifically well suited to these systems. In this paper, we implemented multiple cryptographic algorithms, namely DES, LOKI, DESX, Biham-DES, and SnDES on a reconfigurable hardware so that each algorithm could be replaced by another with low reconfiguration overhead time. The hardware reconfiguration time is about 2.6 ms, which is comparable with the other systems overhead. The main reason for the lower reconfiguration time is that our architecture is partially reconfigurable. Our implementation resulted in a high flexibility but comparable ciphering rate in comparison with previous implementations on field programmable gate arrays (FPGAs). We achieved the ciphering rate of 14080 Mbps on Xilinx 2V6000-5 FPGA.


Reconfigurable Hardware, FPGA, Cryptography