A Novel Methodology for Timing Behavior Recognition of Balanced XOR-XNOR Circuits

A Novel Methodology for Timing Behavior Recognition of Balanced XOR-XNOR Circuits

Tooraj Nikoubin, Keivan Navi, Omid Kavei

Abstract

Since, the characteristics of VLSI basic circuits like XOR/XNOR which are the result of single cell simulation setup, are not necessarily defining their behavior in multistage circuits, so reaching to different test methods and more suitable patterns are important issues for investigators in this field. In this paper a new method is proposed in which timing behavior of different circuits can be determined and compared so the result can be used in different structure configurations and large scale circuits. In addition to the new algorithm for designing XOR/XNOR balance circuits, two more new circuits have been proposed. By simulation tool, HSPICE, first sizing transistor due to PDP characteristics for circuits has been done and then their timing behaviors have been compared. The optimal circuit due to timing behavior is one of the novel methods. Simulations have been done by 0.18µm technology on the base of BS2M3v model.

Keywords

XOR/XNOR, Balanced, Drive Capability, Timing Behavior, Simulation Setup