2004
2
2
55
0
https://jcse.ir/article/96
Design and Analysis of a Fully-Distributed Parallel Packet Switch with Buffered Demultiplexers
0
A Parallel Packet Switch (PPS) is a multistage switch aimed at building a very high-speed switch using much slower devices. A PPS in general has three stages. Several packet switches are placed in the central stage, which operate slower than the external line’s rate. Incoming packets are spread over the center-stage switches by demultiplexers at the input stage. Packets destined to each output port need to be collected and reordered if necessary at the output stage. The initial proposed architecture for the PPS was based on a centralized mechanism with high complexity to distribute incoming packets over the center-stage switches [1]. To reduce the complexity, a distributed algorithm has been proposed in [2] that performs the packet distribution at each demultiplexer independently. The algorithmic complexity of this scheme is in the order of K2 that poses a scalability problem at high speeds as K grows, where K is the number of center-stage switches. In addition, each demultiplexer requires a high-speed buffer at the external line’s rate. In this paper, we have proposed a fully distributed algorithm (at each input line level) with minimal complexity of O(1). Besides demultiplexer buffer in the proposed architecture operates at the low internal link rate. We show that the performance of our architecture is comparable to that of [2]. In particular, we prove that it is stable without any speedup, that is, a bounded delay is guaranteed. The resulting PPS architecture is more simple and implementable.
1
10
Ali
Asghar Khodaparast
ایران
Siavash
Khorsandi
ایران
system design
parallel packet switch
load balancing
synchronization
multistage switch
http://jcse.ir/ow_userfiles/plugins/base/attachments/5bf12db210655_5bf12db21047a.pdf
Computer Society of Iran
Journal on Computer Science and Engineering (JCSE)
2
2
0
https://jcse.ir/article/97
A New Algorithm for Guarding Triangulated Irregular Networks*
0
In this paper, we present a new algorithm for vertex guarding of a triangulated surface, which takes into account the heights of the vertices and considers the global visibility of the guards. In this algorithm, the initial surface is reduced to a collection of simple polygons and trivial triangulated surfaces. This is done by assigning guards to some vertices and removing the faces covered by these guards. The remaining simple regions are then guarded properly. The running time of our algorithm is linear in terms of n, the number of vertices. The upper bound of the assigned guards is [2n / 3], and its expected number is [n/2], which is the same as the worst case lower bound for the problem.
The running time of the best known algorithm for this problem is O(n^(3/2)) which selects at most [n/2] guards. We expect a better performance of our algorithm on the average in practice. This has been verified by experimentation.
1
10
Alireza
Zarei
ایران
Mohammad
Ghodsi
ایران
NP-completeness
art gallery problem
guard set
triangulated irregular networks
approximation algorithms
http://jcse.ir/ow_userfiles/plugins/base/attachments/5bf12eae5d751_5bf12eae5d5c6.pdf
Computer Society of Iran
Journal on Computer Science and Engineering (JCSE)
2
2
0
https://jcse.ir/article/98
A Neural Network Realization of File Transfer Scheduling
0
Neural network models have been successfully applied to solve a variety of problems requiring associative recall, constraint satisfaction, and optimization. This paper presents a new scheduling approach based upon a deterministic modified Hopfield model to solve "File-Transfer" scheduling, an NP-Complete constraint satisfaction problem. The proposed model is mapped onto a 2-dimensional neural network architecture for the transfer scheduling of files between various nodes of a network, by which the overall transfer times is to be minimized. Neural Network-based Scheduling is achieved by formulating the scheduling problem in terms of energy function, and by using the "Motion Equation" corresponding to the variation of energy levels. The main contribution of this work is an efficient and fast parallel algorithm under time and resource constraints, appropriate for implementation on the parallel machines. However, neurons' motion equation is the core of this guided movement mechanism which searches the scheduling space in parallel, and guarantees that the state of system mostly converges to the optimum state. Yet another important contribution of this work is the new strategy of constraints and variables containments by which the performance and efficacy of the system was considerably improved.
1
10
Mohammad
Kazem Akbari
ایران
Seyed
Mehdi Hosseini-nejad
ایران
Mohammad
Kalantari
ایران
neural networks
computer networks
parallel computing
http://jcse.ir/ow_userfiles/plugins/base/attachments/5bf12f03e12ee_5bf12f03e103e.pdf
Computer Society of Iran
Journal on Computer Science and Engineering (JCSE)
2
2
0
https://jcse.ir/article/99
Improved RNS for RSA Hardware Implementation
0
There are many methods for RNS implementation. The Bajard method is the fastest RNS implementation until now. One of the goals of this paper is to optimize this method to achieve higher performance for hardware implementation of RSA cryptosystem. Higher performance means increase in processing speed and less area. Proper hardware architectures for this method are proposed. For this purpose the number of multiplications is the criterion of the processing speed and the required memory for saving the constant values indicates the area required for this system. The number of multiplications is reduced by 400/(3k+11) percent (k is the number of modulus) in the final improved system and the number of constant values reduced by 50 percent.
1
10
Kooroush
Manochehri Kalantari
ایران
Saadat
Pour Mozafari
ایران
Babak
Sadeghiyan
ایران
RNS
RSA
hardware implementation
cryptosystem
modular multiplication
modular exponentiation
http://jcse.ir/ow_userfiles/plugins/base/attachments/5bf12f4ccb29b_5bf12f4ccb00f.pdf
Computer Society of Iran
Journal on Computer Science and Engineering (JCSE)
2
2
0
https://jcse.ir/article/100
Going Meta: Back to the Expectations
0
It is time to use the great implementation achievements and have a look back at the ideas which were treated as pure theory. One of these ideas concerns with metareasoning and it has been under focus in the rest of paper. A classification for types of metareasoning has been proposed. In recent years, only (the ones that here named as) pre-metareasoning and para-metareasoning have been studied. The first one is for predicting the best computation path for having better performance programs. The second, mostly known as interruptible anytime algorithm, is to limit the computation time externally when the approximate answer is better than nothing. One other type of metareasoning (called here as post-meta reasoning) is discussed in a case study. It has been shown as an effective method for reducing error in selflocalization. Post-metareasoning argued as useful when the effectiveness of reasoning methods are not known.
1
10
Shahriar
Pourazin
ایران
Ahmad
Abdollahzadeh Barforoush
ایران
metareasoning
para-metareasoning
pre-metareasoning
post-metareasoning
self-localization
http://jcse.ir/ow_userfiles/plugins/base/attachments/5bf12f8c45a08_5bf12f8c4579f.pdf
Computer Society of Iran
Journal on Computer Science and Engineering (JCSE)
2
2