Using Error Compensation for Defect Tolerance of Nano-Systems*

Using Error Compensation for Defect Tolerance of Nano-Systems*

Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi


As still in infancy, emerging technologies are exhibiting high defect rates; this is mostly due to the stochastic nature of the bottom-up chemical and physical self-assembly processes that are commonly employed in manufacturing. As relationships between components are very complex, a system-level solution is commonly pursued. This challenge is commonly identified with the generic problem of building reliable systems out of unreliable components. In this paper, a novel model which exploits the universality of some circuits (such as a multiplexer), is proposed. In this model a feature that is employed in the presence of errors due to faulty gates, is given by the capability of a restorative stage to have a controlled functional relationship between inputs and the output. Using bifurcation and its geometric representation, the gate error probability is analyzed in detail. Differently from a single gate, the 4-to-1 multiplexer based implementation is considered as instance of a multi-level universal (MLU) circuit. It is proved that in the presence of multiple faulty gates, compensation takes place among them, such that a correct output is still generated at higher threshold failure probability (for a region bounded within the values of 0.471 and 0.523) as compared with previous schemes. Due to its MLU nature, the proposed model operates in a mode that allows generality and flexibility in implementation for threshold analysis.


Fault-Tolerance, Nanotechnology, Bifurcation, Multiplexing, Circuit Model