K2Router: A Low-Power and High-Performance Router Design for Networks-On-Chip

K2Router: A Low-Power and High-Performance Router Design for Networks-On-Chip

Abstract

This paper proposes a new methodology to design of coarse-grained routers in order to improve performance of Networks-on-Chip (NOC). In this approach, several cluster routers in region area of K×K are grouped into one new router called K2Router with similar cost of area and power, however, the performance of whole network is improved. The proposed routers are general in terms of constructions and can be designed and implemented to associate 2×2, 3×3 and 4×4 PEs in a traditional mesh called D2Router, T2Router, and Q2Router, respectively. Based on connections available of such routers, several topologies can be configured. Some of these topologies called DLMesh, DMesh, TLMesh, and QLMesh. Several set of experiments were done on D2Router (k=2), Q2Router (k =4) and O2Router (k=8) with several topologies. The results show that as number of grouped PEs in a K2Router increases, network performance increase dramatically. However, as K increases in K2Router, implementation of the router becomes more complex to use in the network. This is because of wire length in two-dimensional circuit layout, and that would be solved in 3D circuit implementations. Moreover, in the case of using D2Router, the performance, cost and power overhead of DMesh with help of congestion-aware routing algorithm, would be better than those in traditional mesh.

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