A Parallel Architecture for Motion Estimation in HEVC Encoder

A Parallel Architecture for Motion Estimation in HEVC Encoder

Zaid Hanoosh, Hoda Roodaki

Abstract

Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper propose a parallel architecture for motion estimation in HEVC encoder. In the proposed method, the motion estimation part of the encoder which has a high computational complexity, implemented in hardware and the computational complexity of this part is improved using parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

Keywords

Motion Estimation, Parallel Processing, Computational Complexity, HEVC