Architecture-Level Design Space Exploration for Radix-16 Sequential Multipliers
Abstract
Figures of merit of multiplier circuits are greatly influenced by the choice of partial product generation and reduction components and the final product generating adders. In this paper, we focus on radix-16 sequential 32-, 64-, and 128-bit multipliers and study the impact of the aforementioned design options, within a 3-dimensional design space, on the latency, area and energy figures on the synthesized multipliers in 45 nm Nan gate technology. A variety of five different fast final adders and three alternative carry-save adders for partial product reduction contribute to the configuration of the design space, where the delay, power, area, and energy figures for the 45 synthesized multipliers show at least31%, 42%, 20%, and 19% variation from minimum to maximum of the obtained measures. Comparison with the main reference work demonstrates at least 50% speed up, 60% energy improvements.
Keywords
Sequential Multiplier, Design Space Exploration, Adder Architectures, Energy Efficiency
