Stochastic Spintronic Neuron for Hardware Implementation of Neural Networks

Stochastic Spintronic Neuron for Hardware Implementation of Neural Networks

Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari, Masoud Meghdadi


The hardware implementation of neural networks has always been of interest to researchers as it can significantly increase the efficiency and application of neural networks due to the distributed nature of Artificial Neural Networks (ANNs) in both memory and computation. Direct implementation of ANNs also offers large gains when scaling the network sizes. Stochastic neurons are among the most significant aspects of machine learning algorithms and are very important in different neural networks. In this paper, a hardware model for the stochastic neuron based on the two-in-one magnetic tunnel junction (TiO-MTJ) in a subcritical current switching regime is proposed. The use of TiO-MTJ has reduced the area of the proposed neuron and eliminated the risk of MTJ read disturbance. Functional evaluation of the proposed model demonstrates that the behavior of the proposed model is comparable to the mathematical description of the stochastic neuron, and it has a negligible error in comparison with the theoretical model. The simulation results of image binarization over 10,000 images indicate that the proposed hardware model has only 0.25% pack signal-to-noise ratio (PSNR) and 0.02% structural similarity (SSIM) variation compared to its software-based counterpart. The results of corners simulations also show the proper performance of the proposed neuron even in the presence of inevitable major process variations.


Stochastic Neuron, Spintronic, Magnetic Tunnel Junction (MTJ), Neural Networks, Image Binarization


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