Efficient Symmetrical Imprecise 1-Bit Full Adder Cells Using CNFET Technology for Image Processing Applications

Efficient Symmetrical Imprecise 1-Bit Full Adder Cells Using CNFET Technology for Image Processing Applications

Zahra Zareei, Keivan Navi, Midia Reshadi, Peiman Keshavarziyan

Abstract

Nowadays energy consumption in mobile electronic consumers is a serious concern than ever. These devices exploit digital signal processing (DSP) blocks in their structure to perform multimedia algorithms. Since in most cases the output of these blocks is used for humans with limited vision perception, it is feasible to utilize approximate computation methods to enhance circuit parameters such as latency, power consumption, area, etc. In fact, the circuit parameters are enhanced at the expense of making some outputs imprecise. In this paper using the remarkable benefits of carbon nanotube field effect transistors (CNFETs) along with approximate computing method, two novel imprecise Full Adder cells are presented. Extensive simulations at both application and switching levels confirm the supremacy of the proposed cells against their conventional and state-of-the-art counterparts. Moreover, to study the robustness of the proposed cells against process variations, Monte Carlo transient analysis in the presence of carbon nanotube (CNT) diameter variations is performed. Simulation results indicate the robustness of the proposed cells.

Keywords

Approximate Computing; CNFET, Full Adder, Image Processing

References

  • [1] G. E. Moore, "Progress in digital integrated electronics,” in IEEE Solid-State Circuits Society Newsletter, vol. 11, no. 3, pp. 36-37, Sept. 2006.
  • [2] Y. Safaei Mehrabani and M. Eshghi, "Noise and Process Variation Tolerant, Low-Power, High-Speed, and LowEnergy Full Adders in CNFET Technology," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 11, pp. 3268-3281, Nov. 2016.
  • [3] N. H. Bastani, M. H. Moaiyeri, K. Navi, "An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic," Circuits, Systems, and Signal Processing, vol. 37, no. 5, pp. 1863–1883, 2018. Z. Zareei, K. Navi, M. Reshadi, & P. Keshavarziyan: Efficient Symmetrical Imprecise 1-Bit Full Adder Cells Using CNFET Technology for Image Processing Applications (Regular Paper) 59
  • [4] J. Liang, L. Chen, J. Han and F. Lombardi, "Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs," in IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 695-708, July 1 2014.
  • [5] N. Weste and K. Eshraghian, "Principles of CMOS VLSI Design: A System Perspective," Addison-Wesley, Reading, MA, 1993.
  • [6] Y. Safaei Mehrabani, M. Eshghi, "High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells," Journal of Circuits, Systems, and Computers (JCSC), vol. 24, no. 9, pp. 1–24, 2015.
  • [7] J. Han and M. Orshansky, "Approximate computing: An emerging paradigm for energy-efficient design," 2013 18th IEEE European Test Symposium (ETS), Avignon, 2013, pp. 1–6.
  • [8] Y. Safaei Mehrabani, Z. Zareei, and A. Khademzadeh, "A high-speed and high-performance full adder cell based on 32nm CNFET technology for low voltages," Int. J. High Performance Systems Architecture, vol. 4, no. 4, pp. 196–203, 2013.
  • [9] Y. Safaei Mehrabani, R. Faghih Mirzaee, Z. Zareei, S. M. Daryabari, "A Novel High-Speed, Low-Power CNTFETBased Inexact Full Adder Cell for Image Processing Application of Motion Detector," Journal of Circuits, Systems and Computers (JCSC), vol. 26, no. 5, pp. 1–15, 2017.
  • [10] Z. Zareei, K. Navi, and P. Keshavarziyan, "Low-Power, High-Speed 1-Bit Inexact Full Adder Cell Designs Applicable to Low-Energy Image Processing," International Journal of Electronics (IJE), vol. 105, no. 3, pp. 375-384, 2018.
  • [11] Q. Xu, T. Mytkowicz and N. S. Kim, "Approximate Computing: A Survey," in IEEE Design & Test, vol. 33, no. 1, pp. 8-22, Feb. 2016.
  • [12] S. Mittal, "A survey of techniques for approximate computing," ACM Computing Surveys (CSUR), vol. 48, no. 4, pp. 62:1-62:33, 2016.
  • [13] J. Liang, J. Han and F. Lombardi, "New Metrics for the Reliability of Approximate and Probabilistic Adders," in IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760-1771, 2013.
  • [14] Sumio Iijima, "Helical microtubules of graphitic carbon," Nature, vol. 354, pp. 56-58, 1991.
  • [15] H. Terrones, M. Terrones, and J.L. Moran-Lopez, "Curved nanomaterials," Current Science Association, vol. 81, no. 8, pp.1011–1029, 2001.
  • [16] S. Lin, Y. B. Kim and F. Lombardi, "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits," in IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 217-225, March 2011.
  • [17] A. Raychowdhury and K. Roy, "Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2391-2401, Nov. 2007.
  • [18] Yu-Ming Lin, J. Appenzeller, J. Knoch and P. Avouris, "High-performance carbon nanotube field-effect transistor with tunable polarities," in IEEE Transactions on Nanotechnology, vol. 4, no. 5, pp. 481-489, Sept. 2005.
  • [19] J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, "Predicted performance advantages of carbon nanotube transistors with doped nanotubes as source–drain," Phys. Rev. B, 309, cond-mat/0309039, Sep. 2003.
  • [20] J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 1-4, Nov. 2004.
  • [21] Z. Yang, J. Han and F. Lombardi, “Transmission gatebased approximate adders for inexact computing,” IEEE International Symposium on Nanoscale Architectures (NANOARCH), Boston, USA, pp. 145–150, 2015.
  • [22] Z. Yang, A. Jain, J. Liang, J. Han and F. Lombardi, "Approximate XOR/XNOR-based Adders for Inexact Computing," IEEE International Conference on Nanotechnology (IEEE-NANO 2013), Beijing, pp. 690–693, 2013.
  • [23] H. A. F. Almurib, T. N. Kumar and F. Lombardi, "Inexact designs for approximate low power addition by cell replacement," IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, pp. 660–665, 2016.
  • [24] Y. Safaei Mehrabani, M. Eshghi, "A Symmetric, MultiThreshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology," Circuits, Systems, The CSI Journal on Computer Science and Engineering, Vol. 17, No. 2, 2020
  • 60
  • and Signal Processing (CSSP), vol. 34, no. 3, pp. 739–759, 2015.
  • [25] A. K. Singh, H. V. Kumar, G. R. Kadambi, J. K. Kishore,
  • J. Shuttleworth and J. Manikandan, "Quality metrics evaluation of hyperspectral images," Int. Arch. Photogramm. Remote Sens. Spatial Inf. Sci., vol. XL-8, Hyderabad, India, pp. 1221–1226, 2014.
  • [26] J. Deng, H.S.P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part I: model of the intrinsic channel region," IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3186–3194, 2007.
  • [27] J. Deng, H.S.P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part II: full device model and circuit performance benchmarking," IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3195–3205, 2007.
  • [28] G. Cho, Y.B. Kim and F. Lombardi, "Assessment of CNTFET based circuit performance and robustness to PVT variations," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Cancun, pp. 1106-1109, 2009.
  • [29] Y. Safaei Mehrabani, M. H. Shafiabadi, "A novel high-performance and reliable multi-threshold CNFET full adder cell design," Int. J. High Performance Systems Architecture, vol. 7, no. 1, pp. 15-25, 2017.
  • [30] K. El-Shabrawy, K. Maharatna, D. Bagnall, B.M. AlHashimi, "Modeling SWCNT bandgap and effective mass variation using a Monte Carlo approach," IEEE Trans. Nanotechnol., vol. 9, no. 2, pp. 184–193, 2010.