Reducing Access Time in an Object-Oriented ASIP by Splitting Cache Memory

Reducing Access Time in an Object-Oriented ASIP by Splitting Cache Memory

Abstract

In this paper, we have proposed a novel hardware caching technique to reduce the communication latency in ODYSSEY methodology. The main idea is to implement small fast split caches in a parallel way to connect the medium to capture and store ownership information as the data flows from the memory module to the requesting processor. One of the main factors for estimating the rate of modern processors is their memory access time. Using cache memory enhances the access time; therefore it remarkably increases the rate. However, this rate is not sure enough for the systems like ODYSSEY which require parallel memory access time. In this paper, we present a new method in which cache memory is split into parts, so that simultaneous accesses to these parts are possible; therefore, the memory access time is highly improved.

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