A New Register Allocation Method For Testability Improvement
Abstract
Improving testability during the early stages of High-level Synthesis (HLS) has several benefits including reduced test hardwar, overheads, reduced test costs, reduced design iterations, and significant improved fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement. In our register allocation method, several high-level testability parameters including sequential depth, sequential loop, and controllability/observability are considered. Experiments show using this register allocation method results in significant improvement in ATPG time and fault coverage.
Keywords
high-level synthesis, register allocation, conflict graph, weighted graph coloring
