Improving the Retiming Algorithm to Increase the Clock Speed of Synchronous Circuits
Abstract
Retiming algorithms for synchronous circuits are widely used by logic optimizers during the synthesis process. While the algorithm can be used to optimize various aspects of a circuit such as area and power consumption, its prime usage is in cycle time reduction to increase clock speed. However, the original algorithm proposed by Leiserson and Saxe cannot guarantee a cycle time reduction to the extent specified by the designer; and therefore, it has a limited efficacy. In this paper, an improved version of the algorithm is proposed. This version guarantees a cycle time reduction equal to the largest combinatorial delay in the circuit. If the module with the largest combinatorial delay is broken into parts with smaller delays, the improved algorithm can further reduce the cycle time as demonstrated in the paper.
Keywords
retiming, combinational synchronous circuits, speed improvement, functional equivalence
