Integration of CTL, PTL, and DCVSL for Designing a Novel Fast Ternary Half Adder
Abstract
Differential cascode voltage switch logic (DCVSL) is a well-known and practical logic style, which generates two complementary outputs in parallel. High-speed operation is a great advantage of this logic style. This paper presents a novel ternary half adder by integrating capacitive threshold logic (CTL), pass-transistor logic (PTL), and ternary DCVSL. The new design is tested and evaluated by using the CAD tool HSPICE and 32 nanometer CNFET technology. Simulation results demonstrate rapidness and robustness for the proposed ternary half adder. It operates 6.3% faster, and consumes 0.015µW less power than its similar competitor. Moreover, the most beneficial achievement is the elimination of 19 transistors which leads to significant cost and area savings.
Keywords
Half Adder, DCVS, Pass-Transistor Logic, Capacitive Threshold Logic, Ternary Logic, Multiple-Valued Logic, High Speed
